For example, in the technologies relating to semiconductor devices, a main feature of a C-MOS semiconductor circuit lies in the scaling law in which microfabrication of elements improves operating speed and reduces power consumption. Until now, the integration degree and performance per chip have been improved by the microfabrication of elements. However, as the elements are more microfabricated, a tendency in which the improvement in the integration degree and chip performance is slowing down has appeared. Reasons for this include limitations of microfabrication itself, a manifestation of wiring delay among elements due to an improvement in element speed, and an increase in power consumption due to leakage problems caused by the element microfabrication.
On the other hand, when an information processing system of a predetermined scale is to be constructed, since functions that can be integrated on one chip are limited, it is necessary to arrange a plurality of chips and to connect these chips. So far, the direction of arranging chips is horizontal, and a distance of signal transmission among the chips is equal to or longer than one side of a chip. For this reason, even if microfabrication improves the operating speed per chip, transmission among the chips still takes time, and it is therefore difficult to improve the speed as a whole system.
Thus, in order to solve the slowdown in improvement of chip performance and to improve the performance of the entire system, stacked chip systems typified by those described in Japanese Journal of Applied Physics, 40, pp. 3032-3037 (2001) by K. Takahashi et al. (Non-Patent Document 1) and Japanese Unexamined Patent Application Publication No. 2006-330974 (Patent Document 1) have been suggested. This stacked chip system has a structure in which another circuit chip is stacked above and below a circuit chip in a longitudinal direction and the stacked chips are placed on an interposer. In this technology, information and electric power are transmitted among the chips with through vias buried in the chips, through silicon via (TSV) pads, and bumps connecting the chips. By connecting long-distance wirings for signals in the chips and signal wirings among the chips with through vias each straight above the chips, a significant reduction in wiring delay between elements in the chip and interchip transmission delay, which is a bottleneck in the entire system, can be expected. Furthermore, since floating capacitance associated with the wirings among the chips can also be simultaneously reduced, an improvement in signal transmission rate and a reduction in power consumed in transmission can be achieved.
The stacked chip system like this includes the heterogeneous stacking in which chips of different types are stacked and the homogeneous stacking in which the same chips are stacked. As an example of the heterogeneous stacking, a sensor chip system has been suggested. A chip having a sensor integrated thereon is arranged in an uppermost layer, an amplifier and an A/D converter are integrated in a lower layer, and a signal processing circuit and an IO circuit are integrated last. Further, a system in which a memory chip is stacked straight above (or straight below) a processor chip has also been suggested. In these systems, in addition to the reduction in transmission delay and the reduction in transmission electric power described above, a reduction in footprint area in chip vertical mounting and an improvement in band in data transmission by denser connection among the chips than a conventional connection can be expected.
On the other hand, in the homogeneous stacking, stacking of chips of the same type such as field programmable gate array (FPGA) and memory chips has been suggested. These chips have a feature of having a repeated structure even in one chip. In the homogeneous stacking, by increasing the number of stacks while suppressing the mask development cost, an improvement in gate size and memory capacity can be expected. This is referred to as stacking scalability. Further, as with the heterogeneous stacking, an improvement in performance resulting from the reduction in wiring delay and power consumption can also be expected.
Input and output of a signal to and from the stacked chip system are made by accessing a mounting board where this stacked chip system is mounted and a chip of a lowermost or uppermost layer. In practice, a pitch of through vias between stacked chips is several microns to 50 microns, and is narrower than an electrode pitch of BGA or the like used in the connection to the mounting board. For this reason, an interposer for pitch conversion is used. The interposer and the mounting board are connected with bumps. In a chip group constituting stacked chips, a chip in contact with this interposer is an access chip.